Warp Xilinx FPGA IP
The Omnitek Warp IP is a highly optimised FPGA IP-core for creating arbitrary image warps on a real time video stream of up to 4096 x 2160 pixels and up to 60 frames per second. Maximum image quality is achieved through per-pixel filtering and bi-cubic interpolation on 4:4:4 video data at up to 10 bits per colour plane.
Functional block diagram of the Warp IP
The Warp Scaler block manipulates the image either using high level instructions such as rotate, keystone, barrel or a mesh mapping from the Warp load DMA block. The input image is stored and manipulated in external SDRAM via the AXI Interconnect and MIG blocks. The Combiner block combines the Warped image from the Warp Scaler block with a 2D Graphic display from the 2D Graphics Overlay block to create a combined image. The AXI to MIG converter translates the internal AXI bus from the Warp core to the MIG. The MIG (Memory Interface Generator) controls externally connected SDRAM. The DMA Controller provides efficient memory control and arbitrates between ARM processor and Warp memory usage.
Typical Implementation of the Warp IP in a camera Image Signal Processing Pipeline
The diagram above illustrates the use of the Omnitek Warp IP in conjunction with Omnitek's Image Signal Processor (ISP) and HDR Tone-mapping IP to process camera sensor array images. The sensor output is first fed into an ISP pipeline which can crop the image as required, then correct any camera anomalies before it is de-Bayered by the Colour Filter Array block. The image is then passed to our HDR Tone-mapping IP which uses statistical analysis to enhance the image contrast. The image stream is then passed to the Warp Processor to correct for lens distortion and apply any size and shape transformations that are required before the image is output. The system illustrated in the diagram also includes a 2D Graphics Overlay block and a Combiner block to allow graphics to be overlaid on the image.
- Very small resource footprint
- Low latency (from 1 to 1/6th frame depending on transform)
- Efficient external memory interface
- Low Pass Filter coefficient sets available for highest filter quality
- Per-pixel low pass filtering
- Flexible design using Individual IP cores such as the Warp IP, SDI IP, HDMI IP, “LVDS” and V-by-One to suit design and component constraints.
- Optional support for image sizes up to 4096 x 2160 at frame rates up to 60 fps
- Full data buffering to allow input and output to operate in different clock domains
- Fully compatible with other Omnitek IP, such as the ISP IP, OSVP IP Suite, via AXI4-Stream to provide a comprehensive image processing package
The Warp IP can be used in a range of applications including: