V-by-One® Rx &Tx Xilinx FPGA IP
V-by-One® is an electrical digital signalling standard (developed by THine) that can run over inexpensive twisted-pair copper cables. This has been adopted by many display screen manufacturers to interconnect screen technology with electronic circuitry. The Omnitek V-by-One® Tx IP provides a small footprint, highly efficient solution for Xilinx FPGA designs. This IP Core accepts up to a 60-bit wide parallel Xilinx Streaming Video Interface (XSVI) and converts this to a multi lane V-by-One® interface at 8-bit, 10-bit or 12-bit depth for connection to a display device supporting a range of industry pixel mapping methods.
XSVI pixel data is written into the Buffer using the write side clock (xsvi_clk) it is then read out of the Buffer using the phased locked clock (tx_usrclk) which is locked to the output reference clock (refclk). The output of the buffer is passed through a switch to the Packer. This switch allows the data stream to be replaced by a training pattern, if required. The Packer restructures the data that is received in XSVI format into a form ready to be scrambled.
The output of the Scrambler is passed through a switch to the Parallel to Serial converter. This switch allows the data stream to be replaced by a training pattern, if required. The output of the Parallel to Serial converter is a V-by-One serial data stream.
The output reference clock (refclk) is used by the Mixed-Mode Clock Manager (mmcm) to provide a suitable pixel rate clock (pixel_clk) for the XSVI circuitry. The average rate of XSVI clock must be synchronous with the pixel clock. The registers that control the configuration of the V-by-One IP block are accessed via a register bus from a suitable AXI-Lite CPU.
V-by-One® is a registered trademark of Thine, Japan
- Very small FPGA resource foot print
- Very low output latency
- 1 to 16 Lane interface with fully configurable data sampling and section modes
- Support for image sizes up to 4096 x 2160 at frame rates up to 120 fps
- Independent transceiver PHY to allow ease of integration into different designs and packages
- Full data buffering to allow input and output to operate in different clock domains
- Available as an independent IP Core
- Fully integrated into Omnitek’s Projector solution
- Available as reference design
- Fully compatible with other Omnitek IP Cores such as the Omnitek Scalable Video Processor (OSVP)
- Display screen interfaces
- Multi-screen displays
- Interactive display systems
- Monitoring equipment
- Virtual Reality Headsets
- Automotive displays