MPEG 2 Video Decoder FPGA IP

Omnitek’s MPEG 2 Video Decoder FPGA IP has been designed to meet the requirements of the 13818-4 conformance specification, including the requirement to decode ‘constrained parameter’ MPEG1.

Key Features

  • Professional MPEG2 Video decoder firmware for FPGAs or alternative technologies (if required)
  • 27MHz or 148.5MHz processing clock for SD and HD images respectively
  • Efficient external memory interface: SD-SDI decode typically requires a single 8bit interface to DDR2 SDRAM
  • Compliant to ISO13818-2 (ITU-T H.262)
    • 4:2:2Profile@HighLevel
    • 4:2:0 and 4:2:2 format support
    • Up to 2048*1080 resolution
    • I, P and B picture support
    • Field or Frame picture structure
    • Half Pixel prediction accuracy
    • Field, Frame, 16×8 and DualPrime prediction modes
  • FPGA optimised design
  • Inverse DCT optimised for embedded DSP blocks
  • AXI4-Lite memory and control interfaces
  • Validated against ISO13818-4 conformance bit streams
  • Optional ‘System Layer’ extracting timing data
  • Decoder block, System Layer block and wrappers optionally available as source code in either Verilog or VHDL
  • Embedded control software for parsing SI tables available as C++ source code

Deliverables

  • Encrypted netlist or Source code for MPEG2 Decoder Core
  • Software source code for parsing transport stream SI tables (Full package only)
  • Project file/wrapper supporting integration with compatible FPGA components
  • RTL simulation environment (Full package only)
  • Pre-compiled ModelSim libraries for the encrypted parts of the MPEG video decoder (Full package only)
  • Reference design includes drivers and application for Windows® 7™ and XP™

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