Advanced Video Development Platform
Advanced Video Development Platform
Our team of expert consultants have been designing complex signal processing systems using Xilinx FPGAs for over a decade. Our expertise in video algorithm development, PCI-Express interface design, and high-speed memory system implementation has enabled us to produce the Advanced Video Development Platform, specifically targeted at design engineers who need a fast and reliable method to prototype new algorithms and techniques.
The Advanced Video Development Platform is not just a signal processing card. The package also includes an extensive set of VHDL source code for a variety of complex image processing functions, plus a software API and drivers operating under the XP or Vista operating systems.
The card itself is available with a range of Input/Output options, including SD, HD, and "3G" SDI, DVI, HDMI, and analog component or composite video.
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Technical Details
The Advanced Video Development Platform is a powerful, flexible PCI Express-based platform for developing wide range of video products, comprising:
- Video input and video output
- High quality picture scaling
- Motion-adaptive de-interlacing
- Video combining
- Video standard auto-detect
- QDR II SRAM and DDR 2 SDRAM interface and controller
- PCI Express macro interface and DMA controller
Set of VHDL FPGA IP blocks, providing:
- Xilinx Virtex -5 LX50T, SX50T, SX95T or LX110T FPGA with x4 PCI Express macro
- High-speed QDR II SRAM and DDR 2 SDRAM
- Video I/O module supporting two HD / SD / 3G / ASI SDI video inputs and two HD / SD / 3G / ASI SDI video outputs. Interface to main board supports 4 bi-directional serial links and a high speed parallel bus
- Two additional serial ports for cable connection of 4 bi-directional serial links and a control bus.
- Windows XP / Vista Software drivers and Windows XP / Vista GUI interface
...combined into a single reference design that demonstrates all the functionality.
Hardware Components
Xilinx Virtex-5 FPGA
The Advanced Video Development Platform (AVDP) is based around LXT, and SXT versions of the Virtex-5, the latest family of 65 nm FPGAs to be produced by Xilinx. These FPGAs feature advanced on-chip DSP facilities, high-performance parallel SelectIO interface technology and powerful on-chip clock management.
The LXT include MGT serial transceivers with PCI Express and Ethernet hard macros. The SXT range is highly optimized for DSP operations with large amounts internal RAM and multipliers. The PCI Express block is capable of supporting up to 4 lanes of data traffic. The AVDP board is designed for all 1136FFG package parts, i.e. currently LX110T, SX95T, SX50T and LX50T, and instantiates a x4 PCI Express port with a bandwidth of 8Gbits/sec, giving sufficient speed for real time HD video transfer.
1GByte of High-speed DDR 2 SDRAM
The AVDP board includes 1GByte of DDR2 SDRAM, mounted in two 500MByte banks of 64bit-wide data. These can be run at up to 333MHz, corresponding to a data rate of up to 667MHz. Boards fitted with the LX50T or SX50T part, will support only a single bank of DDR2 SDRAM.
4 x 36Mb of High-speed QDR II SRAM
The board also includes 4 x 36Mb QDR II SRAM, running at up to 300MHz and configured in an 18bit-wide bus with a burst of 2. This gives a data rate of up to 600MHz. 72Mb parts may also be fitted to the board. The LX50T version AVDP does not include any SRAM.
Spartan-3 FPGA
The Spartan-3 FPGA included on the AVDP board provides monitor output and parallel I/O to the daughter card. It also provides a low-speed multi-drop parallel bus through which I/O device registers may be controlled. Note: Our lowest cost LX50T AVDP does not include the monitor-out option.
Video I/O Module
Range of video I/O modules, including:
- Dual SDI in/out (SD, HD, "3G", ASI)
- Quad SDI input
- DVI input/output
Serial Ports
Depending on the FPGA used, the AVDP will support either one or two multi-channel MGT serial ports, connected by flexi x4 cables and providing either 4 or 8 bi-directional MGT serial channels.
64Mb Flash PROM
The main role of the Flash PROM is to provide the boot code for the Virtex-5 and Spartan FPGAs. This boot code includes the basic PCI Express interface, which enables the flash to be re-programmed over the PCI Express interface. Once programmed with the boot FPGA, the software may select an alternative FPFA image to load e.g. that required by the application.
Flexible Clock Management
Frequency synthesis enables the clocks to the QDR II SRAM and DDR 2 SDRAM to be selected. Alternatively, the memories may be clocked using frequencies generated in the FPGA. For example, they might be clocked using a synchronous video clock. Clocking for SD, HD and 3G SDI video is generated on the board. The video I/O module also has a clock input and a clock output to enable daughter cards with other clocking standards, such as DVI, to be used.
FPGA IP VHDL Blocks
PCI Express Controller
This block interfaces with the PCI Express hard macro on the Virtex FPGA to provide the I/O for the control register bus and the DMA controller. It encodes and decodes PCI Express packets into master and slave port I/O according to information stored in the base address registers.
DMA Controller
The DMA Controller allows the on-board SRAM and SDRAM to be accessed using multiple simultaneous bus masters. Completely autonomous DMA access is achieved using a scatter/gather list previously assembled on the PC. The register set is based on that of the PLX PCI 9056BA.
SRAM/SDRAM Control & Video Storage
The SDRAM Controller interfaces to the DDR2 SDRAM. It contains the complete SDRAM state machine, including initialisation and calibration control. The DMA controller directly interfaces to a port on this block. The SDRAM Video Storage block provides video frame buffer services, as needed for example by the 2D Resizer block.
The off-chip QDR2 SRAM is driven by the corresponding SRAM Controller block, while the SRAM Video Storage module controls video address generation for the SRAM video I/O
Motion Adaptive De-Interlacer
This block performs fully motion-adaptive de-interlacing of interlaced video. For example, 1080i 60 is converted to 1080p 60.
Motion is detected by identifying luma and chroma differences between pixels in successive frames. The interpolation algorithm used is then determined by comparing these differences against thresholds set, for example, in the light of the noise level associated with the source video signal.
2D Resizer
The 2D Resizer block delivers accurate resizing and aspect ratio change between images of arbitrary size. The data width of the image and the number of resampling / low-pass filter taps used by the Resizer block can be configured to optimise the trade-off between image quality and IP core size.
Input Block
The Input Block provides MGT input interfacing for SD, HD, 3G and ASI SMPTE video. The video is descrambled and the FVH timing reference signals are extracted. This module also provides video standard auto-detection and clock extraction for SD video.
Combiner
This block combines two resized videos and a background video from SRAM into a single video stream in a flexible way, allowing various combinations of Picture in Picture and Picture by Picture to be configured.
Output Block
The Output Block performs SMPTE scrambling and CRC generation for HD video. It also provides the necessary interfacing to the MGT outputs, which for SD video entails repeating the serial stream.
Advanced Video Development Platform Block Diagram
PC Software
Windows XP / Vista Driver
The card is provided with a real-time driver model for Windows XP and Vista, based on the latest driver design methodology. All aspects of the video are controlled using standard DirectShow interfaces. A fully documented API is provided.
Windows XP / Vista GUI
A basic Windows XP / Vista GUI is provided which interfaces to the driver and demonstrates the feature set of the supplied hardware and FPGA IP, including:
- Ability to load and play SD and HD video sequences
- Ability to select between all HD and SD video standards
- GUI control of picture re-size and de-interlace algorithms
- Video proxy display of both video input and video output
- Full transport control of SD and HD video sequences being played
- Record button for recording live input
- Access to low-level hardware registers