Multi-Channel Streaming PCIe DMA Controller for Altera Stratix IV GX and Arria II GX FPGAs

IP Block and Video-Streaming Reference Design

OmniTek’s Multi-Channel Streaming DMA Controller handles data transfer over a PCIe Gen1 or Gen2 bus and is designed for implementation in Altera Stratix IV GX and Arria II GX FPGAs. The Arria II GX FPGA includes a Hard IP block that supports Gen1 PCIe; the Stratix IV GX includes Hard IP blocks supporting both Gen1 and Gen2 PCIe.

The controller offers both memory-based ‘MDMA’ for handling transfers to and from addressed memory such as on-board SRAM and SDRAM, and FIFO-based ‘FDMA’ for streaming applications. The FDMA channels are optimised to transfer video using only FPGA-embedded memory blocks.

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DMA Controller Features

• PCIe-based DMA Controller Core for Altera Stratix IV GX and Arria II GX FLPGAs
• Supports both PCIe Gen1 and PCIe Gen2
  Highly efficient use of PCIe bandwidth (see below), making it particularly suited to data streaming applications
• Configurable for 1, 2, 4 and 8-lane PCIe Gen1 buses and 1, 2 and 4-lane PCIe Gen2 buses (8-lane available on request)
• Supports 32-bit addressing (64-bit addressing to be added soon)
• Configurable number of 32, 64 or 128bit MDMA channels
• Configurable number of 32, 64 or 128bit FDMA streaming channels
• Supplied in SOPC Builder-ready form with Avalon-compatible interfaces and wrapper linking FDMA channels to 20bit Avalon-ST video interfaces
• Controller block, PCIe translation block and wrappers available as source code in either Verilog or VHDL
• Controller IP includes drivers and API for Windows® Vista™ and XP™ (available as C source code)

Video-Streaming Reference Design

Supplied with the DMA Controller is an example videostreaming design. This reference design comprises firmware for implementation on Altera’s Stratix IV GX FPGA AV Dev Kit and an example application written in C++.

The application demonstrates the ability of the DMA controller to read four input video streams at the same time as writing four output video streams, and can work with video in any of the following formats:

• PAL, NTSC
• 1080i (at 50/59.94/60 Hz)
• 720p (at 50/59.94/60 Hz)
• 3G A 1080p (at 50/59.94/60 Hz)

The application also demonstrates the use of the Windows driver and API supplied with the DMA Controller.

The various elements of the Reference Design are also available in source form.

Easy Integration

The DMA Controller is provided as source code in either Verilog or VHDL. Its interfaces are Altera Avaloncompatible to allow easy integration with other Altera SOPC Builder-ready components. Users therefore have the choice of either instantiating the DMA Controller directly in their own top-level design or both configuring it and linking it with other components within SOPC Builder. The top-level module of the Reference Design may also be used within SOPC Builder as the basis for similar designs.

High Bandwidth Efficiency

A major feature of the DMA Controller is its high level of PCIe bus bandwidth efficiency, which it achieves through:

1. Support for multiple outstanding read requests. This minimises the effects of PCIe latency.
2. Pre-fetching of the next descriptor in Scatter-Gather mode to ensure a smooth transition from one descriptor to the next. This is essential when working with streaming video to ensure that buffers do not overflow.
3. Optimisation of the arbiter controlling access to the PCIe bus for back-to-back packing of TLP packets while processing multiple channels.

Example Applications

• Data servers
• Video disk recorders
• Video capture cards

Note: Four-channel operation may require a high-specification graphics card.