• Host board based on Arria II GX EP2AGX125EF35 FPGA, key features of which are its PCIe Gen1 Hard IP block and Nios II embedded processor
• Max® II EPM2210F256 CPLD also on host board
• One HSMC expansion port and one 1GBit Ethernet port on host board
• Video/Audio interfaces as follows:
  • Two SDI inputs and outputs for Triple-rate SDI on HSMC
  • Two AES inputs and outputs on HSMC

• Memory devices as follows included on host board:
  • 128MB 16bit DDR3
  • 1GB 64bit DDR2 SODIMM
  • 2MB SSRAM
  • 64MB Flash memories
• USB and Ethernet cables
• AC adapter power supply
• RoHS compliance

OmniTek’s Multi-Channel Streaming DMA Controller is designed for implementation in Altera FPGAs such as the Arria II that include a PCIe Hard IP block. It supports data transfer over either a PCIe Gen1 (as supported by Arria II FPGAs) or a PCIe Gen2 bus (as supported for example by the Altera Stratix IV FPGA family).

The controller offers both memory-based ‘MDMA’ for handling transfers to and from addressed memory such as on-board SRAM and SDRAM, and FIFO-based ‘FDMA’ for streaming applications. The FDMA channels are optimised to only use FPGA-embedded memory blocks to transfer video.

• Configurable for 1, 2 and 4-lane PCIe Gen1 buses
• Supports 32-bit addressing (with future extension to 64-bit)
• Configurable number of 32, 64 or 128bit MDMA channels
• Configurable number of 32, 64 or 128bit FDMA streaming channels
• Controller block, PCIe translation block and wrappers, optionally available as source code in either Verilog or VHDL
• Controller IP includes drivers and API for Window XP™ and Vista™ (optionally available as C source code)

A major feature of the DMA Controller is its high level of PCIe bus bandwidth efficiency, which it achieves through:

1. Support for multiple outstanding read requests. This
   minimises the effects of PCIe latency.
2. Pre-fetching of the next descriptor in Scatter-Gather mode to ensure a smooth transition from one descriptor to the next. This is essential when working with streaming video to ensure that buffers do not overflow.
3. Optimisation of the arbiter controlling access to the PCIe bus for back-to-back packing of TLP packets while processing multiple channels.

• Data servers
• Video disk recorders
• Video capture cards

The DMA Controller may be provided as source code in either Verilog or VHDL. Its interfaces are Altera Avalon-compatible to allow easy integration with other Altera OpenCore components. Users therefore have the choice of either instantiating the DMA Controller directly in their own top-level design or both configuring it and linking it with other Altera OpenCore components. The top-level module of the Reference Design may also be used as the basis for similar designs.

Included in the development kit is IP both for embedding audio in SD/HD/3G SDI video and for extracting audio embedded in SD and HD SDI video.

The audio embedded by the Embed block is formatted either in accordance with the SMPTE272M standard (for SD video) or in accordance with the SMPTE299M standard (for HD and (provisionally) 3Gb/s video).

The input audio may be at any of the sample rates permitted by the above SMPTE standards and can be provided in either I2S Audio, AES Audio or Parallel Audio format. It can also be either synchronous or asynchronous to the video

The Extract block is designed to extract both audio delivered as SMPTE272M packed data from standard definition SDI and audio delivered as SMPTE299M packed data from high definition SDI. The extracted audio may be output in either I2S Audio, AES Audio, Parallel Audio or Avalon-ST Audio format.

The Embed block allows audio to be embedded in up to 16 channels (8 channel pairs). The Extract block is designed to extract audio from a single channel pair but multiple blocks may beb used together to extract the audio from multiple channel pairs. Operations in both blocks are carried out in accordance with the settings of associated slave registers.

The UDX 2.1 Reference Design illustrates the use of the various image format conversion cores included in Altera's VIP suite to deliver high-quality two-channel up, down and cross conversion of standard definition (SD), high definition (HD) and 3G-SDI video streams. the design handles both interlaced or progressive format video streams.

The design ingests video over two serial digital interface (SDI) channels, then passes it through a series of video and image processing functions provided by the cores of the Altera VIP suite.

A NIOS II processor embedded in the FPGA (also included in the OmniTek Arria II development Kit) provides detailed control over the transformations that take place.

Image format conversion is a commonly-used function in various broadcast infrastructure systems, such as servers, switchers, head-end encoders, and speciality studio displays. the need for image format conversion is driven by the multitude of input image formats that must be converted to HD or a different resolution before they can be stored, encoded or displayed.

SDI Interface

The SDI interface of the reference designs is provided by Altera’s Triple-Speed SDI MegaCore®.

This SDI core comprises receive and transmit blocks that together provide a full-duplex serial digital interface (SDI), working at either 270Mbps for SD, 1.485Gbps for HD video or 2.97Gbps for 3G video.

An important feature of the SDI MegaCore is its ability to auto-switch between these standards, allowing triple-rate SDI on the same FPGA transceiver pin. The core also offers auto-detection of the input video standard.

The Altera Triple-Speed SDI MegaCore is included among the Altera IP offered by OmniTek’s Audio/Video Development Kit for the Altera Arria II GX.

VIP Suite

Altera's Video and Image Processing (VIP) Suite is a collection of MegaCores that provide the various image format conversion facilities required by image processing and display applications, such as video surveillance, broadcast, video conferencing, and medical and military imaging. These cores are also included among the Altera IP offered by OmniTek’s Audio/Video Development Kit for the Altera Arria II GX.

The functions provided by the VIP Suite range from simple building block functions such as colour space conversion to sophisticated video scaling functions that can implement programmable polyphase scaling. The use of these MegaCores is illustrated by the UDX 2.1 Reference Design.

The streaming interfaces on the VIP MegaCores all follow Altera’s Avalon® ST interface standard which makes them easy to use to provide a sequence of format conversion functions.

The following summarises the bandwidth needed by the DMA Controller design to transfer two 1080p60 video streams.

To PC:

• 1080*1920*2*60*2*8 = 3.98 GBits/s
  plus: 0.83 GBits/s to handle read requests
  and: 0.1 Gbits/s to handle scatter-gather
  i.e. total of 4.9 Gbits/s

From PC:

• 1080*1920*2*60*2*(32/3) = 5.3 GBits/s
  plus: 0.1 Gbits/s to handle scatter-gather
  i.e. total of 5.4 Gbits/s

OmniTek is an Altera Certified Design Center